SoCET - System on Chip Extension Technologies
SoCET - System on Chip Extension Technologies
SoCET: The SoCET team provides students with a comprehensive System on Chip design, fabrication and testing that is as similar to industry practice. To be considered, please click for details to complete the SoCET Application.
Advisors:
For inquiries, please email [email protected].
To join SoCET, you will need to complete the application. https://engineering.purdue.edu/SoC-Team.
Description:
This team is eligible for senior design.
The primary objective of the SoCET team is to provide students with a comprehensive System on Chip design, fabrication and test experience that is as similar to industry practice as possible.
Team Structure
SoCET is organized into three distinct levels, allowing students to enter at different points based on their experience:
- STARS: Chip Design Skills
- STARS: Chip Design Project
- SoCET Main
Each section has its own expectations, technical focus, and application process. Students must review the SoCET website to learn about each section and determine which level is appropriate for them.
https://engineering.purdue.edu/SoC-Team
Technologies:
- RISCV open source processor
- Verilog hardware description languages
- FPGA
- UVM (Universal Verification Methodology)
- Verilog/System Verilog coding
- Digital circuit simulation (Modelsim™, Questasim™, NCsim™, others)
- Analog circuit simulation (Spectre™)
- PCB layout
- Transistor level design (Virtuoso™)
- Chip layout (Innovus™ and Virtuoso™
- Git repository management
Prerequisites:
Depends on which aspect of project is of interest- Software design: ECE264 and ECE 362
- Logic design: ECE270, ECE 337 (ECE437 helpful but most haven’t taken yet)
- Transistor and analog design, layout: ECE255, (ECE455/456/559 helpful)
- PCB layout: no prerequisite available. Must be willing to learn.
- Similar experience is acceptable, contact Dr. Johnson ([email protected])
Partners: